Сегодня буду выкладывать вам пару-тройку pdf-ок для факультативного освоения.

Первый в очереди документ 10 летней давности, в котором разобраны отличия SV от V

SystemVerilog is not just for Verification! This paper examines in detail the synthesizable subset of SystemVerilog for ASIC and FPGA designs, and presents the advantages of using these constructs over traditional Verilog. Readers will take away from this paper new RTL modeling skills that will indeed enable modeling with fewer lines of code, while at the same time reducing potential design errors and achieving high synthesis Quality of Results (QoR).

FPGA-Systems Events

sv.pdf

312 KB

Сегодня буду выкладывать вам пару-тройку pdf-ок для факультативного освоения.

Первый в очереди документ 10 летней давности, в котором разобраны отличия SV от V

SystemVerilog is not just for Verification! This paper examines in detail the synthesizable subset of SystemVerilog for ASIC and FPGA designs, and presents the advantages of using these constructs over traditional Verilog. Readers will take away from this paper new RTL modeling skills that will indeed enable modeling with fewer lines of code, while at the same time reducing potential design errors and achieving high synthesis Quality of Results (QoR).

===
@fpgasystems_events - канал плисовых новостей
===

hottg.com/fpgasystems_events/2706

2.2K viewsMichael Korobkov, edited  Apr 26 at 05:31