Experimental High Level Synthesis (HLS) from prototype based object oriented scripting language (Karuta) to RTL (Verilog) which might become useful for FPGA development. Project designed its own language Karuta just only for RTL design instead of reusing existing languages.
>800 commits

Some of following features are incorporated in the language constructs to make it easy to use:

∙ Prototype based object system to model design structures
∙ Flexible data types
◦ Integer with width. Custom operators for defined data types like FP16
∙ Communication primitives
◦ Threads, mailboxes, channels and so on
◦ AXI, RPC like handshake, GPIO, embedded verilog and so on
∙ HDL generators and optimizers
◦ Generates Verilog or HTML
◦ SSA based optimizers
◦ Scheduling and allocation based on device parameters

https://github.com/nlsynth/karuta

#HLS #Karuta #iroha #verilog

FPG𝔸SIC

Experimental High Level Synthesis (HLS) from prototype based object oriented scripting language (Karuta) to RTL (Verilog) which might become useful for FPGA development. Project designed its own language Karuta just only for RTL design instead of reusing existing languages.
>800 commits

Some of following features are incorporated in the language constructs to make it easy to use:

∙ Prototype based object system to model design structures
∙ Flexible data types
◦ Integer with width. Custom operators for defined data types like FP16
∙ Communication primitives
◦ Threads, mailboxes, channels and so on
◦ AXI, RPC like handshake, GPIO, embedded verilog and so on
∙ HDL generators and optimizers
◦ Generates Verilog or HTML
◦ SSA based optimizers
◦ Scheduling and allocation based on device parameters

https://github.com/nlsynth/karuta

#HLS #Karuta #iroha #verilog

hottg.com/fpgasic/57

1.79K viewsedited  Apr 25, 2019 at 18:23