Automated SV Assertion Interface Generator:

It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing assertions.

Features
▫️ Automatically detects the top-level module in the design hierarchy
▫️ Extracts ports and registers from the RTL code
▫️ Handles naming conflicts by using hierarchical paths
▫️ Generates a bind statement for easy integration
▫️ Creates well-formatted and organized interface code
▫️ Supports different modes for interface generation (SPY signals source):
◾️ Ports only (input | output | inout)
◾️ Registers only (signals with "_s" suffix)
◾️ Both ports and registers (default)

Links
💾 https://github.com/Inkub/SV-assertions-IF-generator

#SVA #SV #generator #checker
@fpgasic

FPG𝔸SIC

Automated SV Assertion Interface Generator:

It generates a SV assertion interface for a given RTL design. It analyzes the RTL code to extract ports and registers, and creates an interface that can be used for writing assertions.

Features
▫️ Automatically detects the top-level module in the design hierarchy
▫️ Extracts ports and registers from the RTL code
▫️ Handles naming conflicts by using hierarchical paths
▫️ Generates a bind statement for easy integration
▫️ Creates well-formatted and organized interface code
▫️ Supports different modes for interface generation (SPY signals source):
◾️ Ports only (input | output | inout)
◾️ Registers only (signals with "_s" suffix)
◾️ Both ports and registers (default)

Links
💾 https://github.com/Inkub/SV-assertions-IF-generator

#SVA #SV #generator #checker
@fpgasic

hottg.com/fpgasic/164

1.1K viewsDmitry Murzinov, May 27 at 06:47