OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

FPG𝔸SIC

OpenRAM - an Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.

💾 https://github.com/VLSIDA/OpenRAM

#ASIC #verilog #python #memory #SRAM #generator #GDS #netlist #netgen #magic #Ngspice
@fpgasic

hottg.com/fpgasic/120

2.8K views𝔻𝕠𝕜𝕒, Mar 30, 2021 at 15:48